Vlsi Design Anna University Question Papers For 6th Semester ECE - May / June 2012 Model Previous year Question Paper

VLSI Design Anna University Question Papers For 6th Semester ECE - May / June 2012 Model Previous year Question Paper

Anna University Question Paper VLSI Design  For 6th Semester ECE 

University : Anna University

Subject : EC2354 VLSI Design

Department : 6th Semester ECE

Regulation : 2008

Question Paper : May / June 2013 Model Question Paper

Semester : ECE 6th Semester Question paper

Get More Anna University Question Paper Here

Anna University Chennai � 60 0025

B.E./B.Tech. Degree Examination, May/June 2012

Sixth Semester

Electronics And Communication Engineering

EC 2354/EC 64 � VLSI DESIGN

(Common To PTEC 2354 � VLSI DESIGN For B.E. (Part � Time) Fifth Semester �

Electronics And Communication Engineering Regulation 2009 )

(Regulation 2008)

Time : Three Hours Max:100 Marks

Answer All Questions

Part-A (10 X 2 = 20)

1. Draw The Iv Characteristics Of Mos Transistor. 

2. Brief The Different Operating Regions Of Mos System. 

3. Draw The Equivalent Circuit Structure Of Level 1 Mosfet Model 

In Spice. 

4. Brief About The Variation Of Fringing Field Factor With The  Interconnect Geometry. 

5. Compare Cmos Combinational Logic Gates With Reference To The 

Equivalent N-Mos Depletion Load Logic With Reference To The 

Area Requirement. 

6. What Are The Advantage Of Using A Pseudo N-Mos Gate Instead 

Of A Full Cmos Gate 

7. What Are The Factors That Cause Timing Failures? 

8. What Are The Advantage Of A Single Stuck At Fault? 

9. With Component Instantitation, Write A Vhdl Program For A 

Buffer.  

10. Write A Note On Transport Delay 

Part-B (10 X 2 = 20)

11. (A) Discuss In Detail About: 

 (1) Full-Custom Mask Layout Design (8) 

 (2) Cmos Inverter Layout Design (8) 

[Or]

 (B) (I) With A Neat Diagram Discuss In Detail About Dc Transfer 

Characteristics Of Cmos. (8) 

 (Ii) Write A Short Notes On The Following Along With The Mask 

View 

 (I) Oxide Related Capacitance (4) 

 (Ii) Junction Capacitance (4) 

12. (A) (I) Obtain An Expression For Level 2 Model Equation Of Mosfet 

In Spice. (8) 

 (Ii) Discuss In Detail About: 

 (1) Variation Of Mobility With Electric Field. 

 (2) Variation Of Channel Length In Saturation Modes. 

 (3) Saturation Of Carrier Velocity. (8) 

[Or]

 (B)(I) How Do The Spice Mosfet Model Account For The Parasitic 

Device Capacitances?(8) 

 (Ii) Explain The Charecterization Of Circuits.(8) 

13. (A) (I)For A Two Input Nand Gate Derive An Expression For The Drain 

Current. (8) 

 (Ii) Draw A Cmos Nor2 Gate And Its Complementary Operation 

With Necessary Equations. (4) 

 (Iii) Obtain A Cmos Logic Design Realizing The Boolean Function 

Z=A(D+E)+Bc (8) 

[Or]

(B) (I) Draw A Circuit Diagram Of The Cmos Sr Latch And Explain In 

Detail. (8) 

 (Ii) Along With The Necessary Input And Output Waveforms Of 

The Cmos Dff Negative Edge Triggered Master Slave D Flip Flop. 

(8)  

14. (A) (I) Explain Indetail About Partition And Mux Testing With 

Necessary Example And Diagram. (8) 

 (Ii) Explain The Principle Of Silicon Debug. (8) 

[Or] 

 (B) (I) Elaborate The Scan Based Techniques. (8) 

 (Ii) Discuss In Detail About: 

 (I) Pseudo Random Pattern Generator. (4) 

 (Ii) Output Response Analyser. (4) 

15. (A) Using Mixed Level Mode Write A Vhdl Program For A 

 (I) Comparator. (8) 

 (Ii) D �Flip Flop. (8) 

[Or]

 (B) With All The Three Types Of Modeling Write A Vhdl  Program For A 

 (I) Decoder (8) 

 (Ii) Full Adder. (8) 

VLSI Design Anna University Question Papers for 6th Semester ECE